Resistive Random Access Memories (RRAM) are today the subject of great interest, particularly on account of their low electrical consumption and their high operating speed.
A resistive type memory cell has at least two states: a “High Resistance State” (HRS), also called “OFF” state, and a “Low Resistance State” (LRS) or “ON” state. It may thus be used to store binary information.
Three types of resistive memories may be distinguished: memories based on thermochemical mechanism, memories based on valence change, and memories based on electrochemical metallisation.
The field of the present invention more particularly relates to this latter category based on ion conduction materials (CBRAM or “Conductive Bridging RAM” memories). The operation resides in the reversible formation and rupture of a conductive filament in a solid electrolyte, through dissolution of a soluble electrode. These memories are promising due to their low programming voltages (of the order of a Volt), their short programming times (<1 μs), their low consumption and their low integration cost. Furthermore, these memories can be integrated into the metallisation levels of the logic of a circuit (“above IC”), which makes it possible to increase the integration density of the circuit. From the architectural viewpoint, they only require a selection device, a transistor or a diode for example.
The operation of CBRAM memories is based on the formation, within a solid electrolyte, of one or more metal filaments (also called “dendrites”) between two electrodes, when the electrodes are taken to suitable potentials. The formation of the filament makes it possible to obtain a given electrical conduction between the two electrodes. By modifying the potentials applied to the electrodes, it is possible to modify the distribution of the filament, and thus to modify the electrical conduction between the two electrodes. For example, by reversing the potential between the electrodes, it is possible to make disappear or reduce the metal filament, so as to eliminate or reduce considerably the electrical conduction due to the presence of the filament.
FIGS. 1A and 1B are schematic diagrams of a CBRAM type memory device 1, respectively in the “OFF” state, and in the “ON” state.
This device 1 is formed by a Metal/Ion conductor/Metal type stack. It comprises a solid electrolyte 2, for example based on doped chalcogenide (e.g. GeS) or oxide (e.g. Al2O3). The electrolyte 2 is arranged between a lower electrode 3, for example made of Pt, forming an inert cathode, and an upper electrode 4 comprising a portion of ionisable metal, for example copper, and forming an anode. A portion of ionisable metal is a portion of metal able to form metal ions (here Cu2+ ions) when it is subjected to a suitable electrical potential. The device 1 represented in FIG. 1A or 1B typically forms a memory point, that is to say a unit memory cell, of a memory comprising a multitude of these memory devices.
As indicated previously, the memory state of a CBRAM memory device results from the difference in electrical resistivity between two states: “ON” and “OFF”.
In the “OFF” state (FIG. 1A), the metal ions (here Cu2+ ions for a soluble electrode comprising Cu) coming from the portion of ionisable metal are dispersed throughout the solid electrolyte 2. Thus, no electrical contact is established between the cathode 3 and the anode 4, that is to say between the upper electrode and the lower electrode. The solid electrolyte comprises an electrically insulating zone of high resistivity between the anode and the cathode.
When a positive potential V is applied to the upper soluble electrode 4 (the anode), an oxidation-reduction reaction takes place at the electrode, creating mobile ions 5 (FIG. 1A). In the case of a copper electrode 4, the following reaction takes place:Cu→Cu2++2e−.
The ions 5 then move in the electrolyte 2 under the effect of the electrical field applied to the electrodes. The speed of movement depends on the mobility of the ion in the electrolyte in question, which guides the choice of the soluble electrode/electrolyte pairing (examples: Ag/GeS; Cu/Al2O3, etc.). The speeds of movement of the ions are of the order of nm/ns.
On arrival at the inert electrode 3 (the cathode), the ions 5 are reduced due to the presence of electrons supplied by the electrode 3, leading to the growth of a metal filament 6 according to the following reaction:Cu2+2e−→Cu
The filament 6 grows preferentially in the direction of the soluble electrode 4.
The memory 1 then passes to the “ON” state (FIG. 1B) when the filament 6 enables contact between the electrodes 3 and 4, making the stack conductive. This phase is called “SET” of the memory.
To pass to the “OFF” state (“RESET” phase of the memory), a negative voltage V is applied to the upper electrode 4, leading to the dissolution of the conductive filament. To justify this dissolution, thermal (heating) and oxidation-reduction mechanisms are generally put forward. More precisely, the step consisting in writing for the first time the memory 1, that is to say forming for the first time the filament in the electrolyte 2 of the memory 1, is called “forming”. “SET” is thus taken to mean the step of formation of the filament 6 carried out after at least one first erasing of the memory cell, that is to say after the filament of the memory cell has at least been formed a first time (forming step) then dissolved (RESET step).
Often, the electrolyte 2 contains in the “OFF” state a residual filament 6 in contact with the cathode 3. This stems from the preceding SET phase and has not been dissolved completely during the RESET of the memory. The filament is designated residual when it does not establish a sufficient electrical conduction between the electrodes to obtain the “ON” state.
An area of development for CBRAM memories relates to the widening of the memory window; the latter is defined as the ratio between the resistances of the insulating “OFF” and “ON” states, that is to say the ratio Roff/Ron. The higher this ratio, the easier it is to distinguish the two logic states “OFF” and “ON” of the CBRAM memory. A wide window even makes it possible to envisage multi-bit coding, that is to say to obtain more than two states with a single memory cell using several levels (i.e. at least 3) of resistance.